Receiver

ABSTRACT

To provide a receiver not requiring any large circuit. A carrier-wave-phase-error table  15 - 1 A for BPSK modulation in which a range equal to or more than 0 of I-axis is defined is prepared for a carrier-wave regenerating circuit  10 A of a demodulating circuit  1 A for orthogonally detecting a received signal in which digital signals according to BPSK, QPSK, and 8PSK modulations are time-multiplexed and outputting I and Q symbol-stream data I t  and Q t  for each symbol. When a remapper  7 A outputs I 0t  and Q 0t  obtained by inversely phase-rotating I t  and Q t  by −Θ against a received-signal-phase rotation angle Θ and generating an absolute phase of I t  and Q t , a phase-error detecting circuit  70  obtains a shift angle Θ′ up to a target phase convergent angle of a received-signal point shown by I 0t  and Q 0t  viewed in the positive direction of I-axis according to a modulation system currently demodulated, reads phase error data corresponding to I 1t  and Q 1t  obtained by phase-rotating I t  and Q t  by −(Θ+Θ′) by the remapper  7 A through time sharing out of the table  15 - 1 A, and corrects a phase of a reference carrier wave so that the phase error data becomes zero.

TECHNICAL FIELD

The present invention relates to a receiver, particularly to a receiverfor demodulating a signal to be PSK-modulated in which digital signalsmodulated by 2-, 4-, and 8-phase PSK modulation systems aretime-multiplexed in accordance with a hierarchical transmission systemor the like by using a carrier wave regenerated by carrier-waveregenerating means to output I and Q symbol-stream data.

BACKGROUND ART

Practical use of digital satellite TV broadcast is advanced whichconforms to a plurality of modulation systems having necessary C/Nsdifferent from each other such as hierarchical transmission systems inwhich a wave to be 8PSK-modulated, a wave to be QPSK-modulated, and awave to be BPSK-modulated are time-multiplexed and repeatedlytransmitted with frame.

FIG. 11(1) is an illustration showing a frame configuration of ahierarchical transmission system. One frame is configured by aframe-synchronizing-signal pattern comprising 32 BPSK-modulated symbols(20 latter-half symbols among 32 symbols are actually used asframe-synchronizing signal), a TMCC (Transmission and MultiplexingConfiguration Control) pattern comprising 128 BPSK-modulated symbols toidentify a multiple transmission configuration, a super-frameidentifying signal pattern comprising 32 symbols (20 latter-half symbolsamong 32 symbols are actually used as super-frame identifying signal), amain signal of 203 8PSK(trellis-codec-8PSK)-modulated symbols, a burstsymbol signal (BS) of four symbols in which a pseudo random noise (PN)signal is BPSK-modulated, a main signal of 2028PSK(trellis-codec-8PSK)-modulated symbols, a burst symbol signal (BS)of four symbols in which a pseudo random noise (PN) signal isBPSK-modulated, . . . , a main signal of 203 QPSK-modulated symbols, aburst symbol signal (BS) of four symbols in which a pseudo random noise(PN) signal is BPSK-modulated, a main signal of 203 QPSK-modulatedsymbols, and a burst symbol signal (BS) of four BPSK-modulated symbolsin order.

In case of a receiver for receiving a digital wave to be modulated (waveto be PSK-modulated) according to a hierarchical transmission system, anintermediate-frequency signal of received signals received by areceiving circuit is demodulated by a demodulating circuit andtwo-series I and Q base-band signals (hereafter, I and Q base-bandsignals are also referred to as I and Q symbol-stream data) showinginstantaneous values of I-axis and Q-axis orthogonal to each other foreach symbol are obtained. Absolute phase generation to be fitted to atransmission-signal phase angle is performed by an absolute-phasegenerating circuit by acquiring a frame-synchronizing signal from thedemodulated I and Q base-band signals, obtaining the presentreceived-signal-phase rotation angle from a signal point arrangement ofthe acquired frame-synchronizing signal, and inversely rotating thephase of the demodulated I and Q base-band signals on the basis of theobtained received-signal phase rotation angle.

As shown in FIG. 12, an absolute-phase generating circuit of a receiverfor receiving a wave to be PSK-modulated according to a conventionalhierarchical transmission system is configured by a frame-syncdetecting/regenerating circuit 2 serving as frame-synchronizing-signalacquiring means provided for the output side of a demodulating circuit 1to acquire a frame-synchronizing signal, a remapper 7 serving asinversely-phase-rotating means comprising a ROM, and areceived-signal-phase-rotation-angle detecting circuit 8 serving asreceived-signal-phase-rotation-angle detecting means. Symbol 9 denotes atransmission-configuration identifying circuit for identifying themultiple transmission configuration shown in FIG. 11(1), which outputs atwo-bit modulation-system identifying signal DM.

The demodulating circuit 1 orthogonally detects intermediate-frequencysignals to obtain I and Q base-band signals. In the demodulating circuit1, symbol 10 denotes a carrier-wave regenerating circuit to regeneratetwo reference carrier waves f_(c1) (=cosωt) and f_(c2) (=sinωt)orthogonal to each other with phases shifted from each other by 90°because a frequency and a phase synchronize with a carrier wave beforemodulated in inputs of the demodulating circuit 1. Symbols 60 and 61denote multipliers for multiplying an intermediate-frequency signal IFby f_(c1) and f_(c2), 62 and 63 denote A/D converters for A/D-convertingoutputs of the multipliers 60 and 61 at a sampling rate two times largerthan a symbol rate, 64 and 65 denote digital filters for applying bandrestriction to outputs of the A/D converters 62 and 63 throughdigital-signal processing, 66 and 67 denote thinning circuits forthinning outputs of the digital filters 64 and 65 to 1/2 sampling rateand outputting two series of I and Q base-band signals (I and Qsymbol-stream data) showing instantaneous values of I-axis and Q-axisfor each symbol. The thinning circuits 66 and 67 transmit two series ofI and Q base-band signals I(8) and Q(8) (a numeral in parenthesesdenotes the number of quantization bits which is hereafter also simplyreferred to as I and Q) respectively having 8 quantization bits (two'scomplement system).

Mapping for each modulation system at the transmission side is describedbelow by referring to FIGS. 13(1) to 13(3). FIG. 13(1) shows signalpoint arrangements on I-Q phase plane (also referred to as I-Q vectorplane or I-Q signal space diagram) when using 8PSK for a modulationsystem. The 8PSK modulation system transmits a three-bit digital signal(abc) by one symbol. Combinations of bits constituting the symbolinclude such eight ways as (000), (001), (010), (011), (100), (101),(110), and (111). These three-bit digital signals are converted intosignal point arrangements “0” to “7” on transmission-side I-Q phaseplane in FIG. 12(1) and this conversion is referred to as 8PSK mapping.

In case of the example shown in FIG. 13(1), bit string (000) isconverted into signal point arrangement “0,” bit string (001) intosignal point arrangement “1,” bit string (011) into signal pointarrangement “2,” bit string (010) into signal point arrangement “3,” bitstring (100) into signal point arrangement “4,” bit string (101) intosignal point arrangement “5,” bit string (111) into signal pointarrangement “6,” and bit string (110) into signal point arrangement “7.”

FIG. 13(2) shows signal point arrangements on I-Q phase plane at thetime of using QPSK for a modulation system. The QPSK modulation systemtransmits two-bit digital signal (de) by one symbol. Combinations ofbits constituting the symbol include such four ways as (00), (01), (10),and (11). In the case of the example in FIG. 13(2), bit string (00) isconverted into signal point arrangement “1,” bit string (01) into signalpoint arrangement “3,” bit string (11) into signal point arrangement“5,” and bit string (10) into signal point arrangement “7.”

FIG. 13(3) shows signal point arrangements at the time of using BPSK fora modulation system. The BPSK modulation system transmits one-bitdigital signal (f) by one symbol. In case of the digital signal (f), bit(0) is converted into signal point arrangement “0” and bit (1) intosignal point arrangement “4.” The relation between signal pointarrangement and arrangement number is the same for various modulationsystems on the basis of 8BPSK.

I-axis and Q-axis of QPSK and BPSK in a hierarchical transmission systemcoincide with I-axis and Q-axis of 8PSK.

When a phase of a carrier wave before modulated in inputs of thedemodulating circuit 1 coincides with phases of reference carrier wavesf_(c1) and f_(c2) regenerated by the carrier-wave regenerating circuit10, a phase of a received-signal point on I-Q phase plane according toreception-side I and Q base-band signals I(8) and Q(8) when receivingdigital signals related to signal point arrangements “0” to “7” on I-Qphase plane at the transmission side coincides with that of thetransmission side. Therefore, by directly using the relation betweensignal point arrangement and digital signal at the transmission side(refer to FIG. 13), it is possible to correctly identify a digitalsignal received from a signal point arrangement of a received-signalpoint.

However, because the reference carrier waves f_(c1) and f_(c2) canactually take various phase states for a carrier wave before modulatedin inputs of the demodulating circuit 1, a received-signal point at thereception side has a phase position rotated by a certain angle θ againstthe transmission side. Moreover, when a phase of a carrier wave beforemodulated in inputs of the demodulating circuit 1 fluctuates, e alsofluctuates. When a phase of a received-signal point rotates against thetransmission side at random, it is impossible to identify a receiveddigital signal. For example, when θ is equal to π/8, a received-signalpoint of a digital signal (000) of a signal point arrangement “0”according to a transmission-side 8PSK modulation system is brought tothe middle between signal point arrangements “0” and “1” at thereception side. Therefore, at the time of assuming that the digitalsignal (000) is received at the signal point arrangement “0,” it isjudged that the signal is correctly received. However, at the time ofassuming that the signal is received at the signal point arrangement“1,” it is erroneously judged that a digital signal (001) is received.Therefore, the carrier-wave regenerating circuit 10 corrects phases ofthe reference carrier waves f_(c1) and f_(c2) so that a received-signalpoint keeps a certain rotation angle against the transmission side and adigital signal is correctly identified.

Specifically, the reference carrier wave f_(c1) is generated by making aVCO (voltage control oscillator) 11 of the carrier-wave regeneratingcircuit 10 oscillate at a transmission-carrier-wave frequency and thereference carrier wave f_(c2) is generated by delaying a phase of anoscillation signal of the VCO 11 by 90° by a 90° phase shifter 12.Moreover, by changing a control voltage of the VCO 11, it is possible tochange phases of the reference carrier waves f_(c1) and f_(c2).

The carrier-wave regenerating circuit 10 is provided with phase errortables 13, 14-1 and 14-2, and 15-1 to 15-4 obtained by tabulatingrelations between various data sets of I and Q base-band signals I(8)and Q(8) and carrier-wave-phase-error data (hereafter also referred toas phase error data) Δφ(8) of eight quantization bits (two's complementsystem) and respectively configured by a ROM for each of 8PSK, QPSK, andBPSK modulation systems (refer to FIG. 14). I and Q base-band signalsI(8) and Q(8) are input to the phase error tables 13, 14-1 and 14-2, and15-1 to 15-4 in parallel. A phase error table selectively enabled by aselector to be described later outputs phase error data Δφ(8)corresponding to I and Q base-band signals I(8) and Q(8) input from thedemodulating circuit 1.

The phase error table 13 is used for 8PSK, in which the relation betweenphase angle φ (refer to FIG. 15) and phase error data Δφ(8) of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)in symbols input from the demodulating circuit 1 on I-Q phase plane isconstituted as shown in FIG. 17. A selector 16 enables (activates) onlythe phase error table 13 while the demodulating circuit 1 demodulatesdigital waves to be modulated according to the BPSK modulation system(designated by a modulation-system identifying signal DM output from atransmission-configuration identifying circuit 9 to be described later)in accordance with a clock CLK_(SYB) (refer to FIG. 11(2)) at a symbolrate synchronous with outputs of I and Q base-band signals I(8) and Q(8)output from the demodulating circuit 1 and reads phase error data Δφ(8)corresponding to the set data of I and Q base-band signals I(8) and Q(8)whenever the demodulating circuit 1 outputs the I(8) and Q(8) for onesymbol.

The phase error data Δφ(8) is converted into a phase error voltage by aD/A converter 17 and then, low-frequency components of the data areremoved by an LPF 18 and the data is applied to the VCO 11 as a controlvoltage. When the phase error data Δφ(8) is equal to 0, outputs of theLPF 18 are not changed and therefore, phases of the reference carrierwaves f_(c1) and f_(c2) are not changed. However, when the phase errordata Δφ(8) is positive, an output of the LPF 18 is strengthened andphases of the reference carrier waves f_(c1) and f_(c2) are delayed.However, when the phase error data Δφ(8) is negative, an output of theLPF 18 is weakened and phases of the reference carrier waves f_(c1) andf_(c2) are advanced.

In the phase error table 13, when a modulation system is 8PSK, thedifference between a phase angle φ of a received-signal point shown by Iand Q base-band signals I(8) and Q(8) and a phase of the nearest one(which is a target phase convergent angle of the received-signal point)of signal point arrangements “0” to “7” is equal to phase error dataΔφ(8). In this connection, in FIG. 15, when the received-signal point isincluded in a certain area DR_(i) among areas DR₀ to DR₇ obtained bydividing I-Q phase plane into eight sub-planes so that phases 0, π/4,2π/4, 3π/4, 4π/4, 5π/4, 6π/4, and 7π/4 of signal point arrangements “0”to “7” respectively become a center, a target phase convergent angle ofthe received-signal point based on phase correction of the referencecarrier waves f_(c1) and f_(c2) becomes equal to i·(π/4).

Therefore, digital signals of signal point arrangements of phases 0,π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4, and 7π/4 according to the 8PSKmodulation system at the transmission side respectively converge into aposition rotated by Θ=m×π/4 (m is any one of integers 0 to 7; refer toFIG. 16) on I-Q phase plane at the reception side. Symbol Θ denotes aphase rotation angle of a received-signal point against a transmissionsignal (also in the case of QPSK and BPSK, a received-signal-phaserotation angle is equal to Θ same as the case of 8PSK). Thereby, becausea received-signal point according to the 8PSK modulation system isbrought to any one of positions of phases 0, π/4, 2π/4, 3π/4, 4π/4,5π/4, 6π/4, and 7π/4, signal point arrangements “0” to “7” on I-Q phaseplane at the reception side have the same arrangements as thetransmission side as a whole (however, the relation between individualsignal point arrangement and digital signal depends on Θ). By detectingΘ and inversely rotating a phase by −Θ, the relation between signalpoint arrangement and digital signal can be made same as that of thetransmission side (absolute phase generation) and a received digitalsignal can be easily identified.

The phase error tables 14-1 and 14-2 are used for QPSK, in which therelation between phase angle φ and phase error data Δφ(8) of a receivedsignal point shown by I and Q base-band signals I(8) and Q(8) in symbolson I-Q phase plane is constituted as shown in FIGS. 18 and 19. Undernormal reception, the selector 16 enables only the phase error table14-1 when a received-signal-phase rotation angle Θ is equal to 0, 2π/4,4π/4, or 6π/4 while the demodulating circuit 1 demodulates digital wavesto be modulated according to the QPSK modulation system in accordancewith a clock CLK_(SYB) at a symbol rate and reads phase error data Δφ(8)corresponding to the set data of I and Q base-band signals I(8) and Q(8)out of the phase error table 14-1 whenever the demodulating circuit 1outputs the I(8) and Q(8) for one symbol.

The phase error table 14-1 is used when a modulation system uses QPSKand a received-signal-phase rotation angle Θ is equal to any one of 0,2π/4, 4π/4, and 6π/4, in which the difference between a phase angle φ ofa received-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase-convergent angleof the received-signal point) of signal point arrangements “1,” “3,”“5,” and “7” is equal to phase error data Δφ. In this connection, asshown in FIG. 20(1), when the received-signal point is included in anarea ER_(i) among areas ER₀ to ER₃ obtained by dividing I-Q phase planeinto four sub-planes so that phases π/4, 3π/4, 5π/4, and 7π/4 of signalpoints arrangements “1,” “3,” “5,” and “7” respectively become a center,the target phase convergent angle is equal to i·(2π/4)+π/4.

Therefore, digital signals of signal point arrangements “1,” “3,” “5,”and “7” of phases π/4, 3π/4, 5π/4, and 7π/4 according to the QPSKmodulation system at the transmission side respectively converge into aposition rotated by the above angle Θ on I-Q phase plane at thereception side. When Θ is equal to 0, 2π/4, 4π/4, or 6π/4, areceived-signal point according to the QPSK modulation system is broughtto any one of positions of phases π/4, 3π/4, 5π/4 and 7π/4. By detectingΘ and inversely rotating a phase by −Θ, the relation between signalpoint arrangement and digital signal can be made the same as that of thetransmission side (absolute phase generation) and a received digitalsignal can be easily identified.

Moreover, the selector 16 enables only the phase error table 14-2 when Θis equal to π/4, 3π/4, 5π/4, or 7π/4 while the demodulating circuit 10demodulates digital waves to be modulated according to the QPSKmodulation system and reads phase error data Δφ(8) corresponding to theset data of I and Q base-band signals I(8) and Q(8) out of the phaseerror table 14-2 whenever the demodulating circuit 1 outputs the I(8)and Q(8) for one symbol.

The phase error table 14-2 is used when a modulation system uses QPSKand a received-signal-phase rotation angle Θ is equal to any one of π/4,3π/4, 5π/4, and 7π/4, in which the difference between a phase angle φ ofa received-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase convergent angleof the received-signal point) of signal point arrangements “0,” “2,”“4,” and “6” is equal to phase error data Δφ. In this connection, asshown in FIG. 20(2), when the received-signal point is included in anarea FR_(i) among areas FR₀ to FR₃ obtained by dividing I-Q phase planeinto four sub-planes so that phases 0, 2π/4, 4π/4 and 6π/4 of signalpoint arrangements “0,” “2,” “4,” and “6” respectively become a center,the target phase convergent angle is equal to i·(2π/4).

Therefore, digital signals of signal point arrangements “1,” “3,” “5,”and “7” of phases π/4, 3π/4, 5π/4 and 7π/4 according to the QPSKmodulation system at the transmission side respectively converge into aposition rotated by the above angle Θ on I-Q phase plane at thereception side. When Θ is equal to π/4, 3π/4, 5π/4, or 7π/4, eachreceived-signal point according to the QPSK modulation system is broughtto any one of positions of phases 0, 2π/4, 4π/4, and 6π/4. By detectingΘ and inversely rotating a phase by −Θ, the same phase as that of thetransmission side is realized (absolute phase generation), the relationbetween signal point arrangement and digital signal can be made the sameas that of the transmission side, and a received digital signal can beeasily identified.

The phase error tables 15-1 to 15-4 are used for BPSK, in which therelation between phase angle φ and phase error data Δφ(8) of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)on I-Q phase plane is constituted as shown in FIGS. 21 to 24. Theselector 16 enables only the phase error table 15-1 when areceived-signal-phase rotation angle Θ due to phase correction of an8PSK modulation portion is equal to 0 or 4π/4 while the demodulatingcircuit 1 demodulates digital waves to be modulated according to theBPSK modulation system synchronously with a clock CLK_(SYB) at a symbolrate and reads phase error data Δφ(8) corresponding to the set data of Iand Q base-band signals I(8) and Q(8) out of the phase error table 15-1whenever the demodulating circuit 1 outputs the I(8) and Q(8) for onesymbol.

The phase error table 15-1 is used when a modulation system uses BPSKand a received-signal-phase rotation angle Θ is equal to either of 0 and4π/4, in which the difference between a phase angle φ of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase convergent angleof the received-signal point) of signal point arrangements “0” and “4”is equal to phase error data Δφ. In this connection, as shown in FIG.25(1), when the received-signal point is included in the area GR_(i) ofareas GR₀ and GR₁ obtained by dividing I-Q phase plane into twosub-planes so that phases 0 and 4π/4 of signal point arrangements “0”and “4” respectively become a center, the target phase convergent angleis equal to i·(4π/4).

Therefore, digital signals of signal point arrangements “0” and “4” ofphases 0 and 4π/4 according to the BPSK modulation system at thetransmission side respectively converge into a position rotated by theabove angle Θ on reception-side I-Q phase plane. When Θ is equal to 0 or4π/4, a received-signal point according to the BPSK modulation system isbrought to either of positions of phases 0 and 4π/4.

Moreover, the selector 16 enables only the phase error table 15-2 when Θis equal to π/4 or 5π/4 while demodulating a digital wave to bemodulated according to the BPSK modulation system and reads phase errordata Δφ(8) corresponding to I and Q base-band signals I(8) and Q(8) outof the phase error table 15-2 whenever the demodulating circuit 1outputs the I(8) and Q(8) for one symbol.

The phase error table 15-2 is used when a modulation system uses BPSKand a received-signal-phase rotation angle Θ is equal to either of π/4and 5π/4, in which the difference between a phase angle φ of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase convergent angleof the received-signal point) of signal point arrangements “1” and “5”is equal to phase error data Δφ. In this connection, as shown in FIG.25(2), when the received-signal point is included in the area HR₁ ofareas HR₀ and HR₁ obtained by dividing I-Q phase plane into twosub-planes so that phases π/4 and 7π/4 of signal point arrangements “1”and “5” respectively become a center, the target phase convergent angleis equal to i·(4π/4)+π/4.

Thus, digital signals of signal point arrangements “0” and “4” of phases0 and 4π/4 according to the BPSK modulation system at the transmissionside respectively converge into a position rotated by the above angle Θon I-Q phase plane at the reception side. When Θ is equal to π/4 or5π/4, a received-signal point according to the BPSK modulation system isbrought to either of positions of phases π/4 and 5π/4.

Moreover, the selector 16 enables only the phase error table 15-3 when Θis equal to 2π/4 or 6π/4 while demodulating a digital wave to bemodulated according to the BPSK modulation system and reads phase errordata Δφ(8) corresponding to the set data of I and Q base-band signalsI(8) and Q(8) out of the phase error table 15-3 whenever thedemodulating circuit 1 outputs the I(8) and Q(8) for one symbol.

The phase error table 15-3 is used when a modulation system uses BPSKand a received-signal-phase rotation angle Θ is equal to either of 2π/4and 6π/4, in which the difference between a phase angle φ of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase convergent angleof the received-signal point) of signal point arrangements “2” and “6”is equal to phase error data Δφ. In this connection, as shown in FIG.25(3), when the received-signal point is included in the area IR_(i) ofareas IR₀ and IR₁ obtained by dividing I-Q phase plane into twosub-planes so that phases 2π/4 and 6π/4 of signal point arrangements “2”and “6” respectively become a center, the target phase convergent angleis equal to i·(4π/4)+2π/4.

Therefore, digital signals of signal point arrangements “0” and “4” ofphases 0 and 4π/4 according to the BPSK modulation system at thetransmission side respectively converge into a position rotated by theabove angle Θ on reception-side I-Q phase plane. When Θ is equal to 2π/4or 6π/4, a received-signal point according to the BPSK modulation systemis brought to either of positions of phases 2π/4 and 6π/4.

Moreover, the selector 16 enables only the phase error table 15-4 when Θis equal to 3π/4 or 7π/4 while demodulating a digital wave to bemodulated according to the BPSK modulation system and reads phase errordata Δφ(8) corresponding to the set data of I and Q base-band signalsI(8) and Q(8) out of the phase error table 15-4 whenever thedemodulating circuit 1 outputs the I(8) and Q(8) for one symbol.

The phase error table 15-4 is used when a modulation system uses BPSKand a received-signal-phase rotation angle Θ is equal to either of 3π/4and 7π/4, in which the difference between a phase angle φ of areceived-signal point shown by I and Q base-band signals I(8) and Q(8)and a phase of the nearest one (which is a target phase convergent angleof the received-signal point) of signal point arrangements “3” and “7”is equal to phase error data Δφ. In this connection, as shown in FIG.25(4), when the received-signal point is included in an area JR_(i) ofareas JR₀ and JR₁ obtained by dividing I-Q phase plane into twosub-planes so that phases 3π/4 and 7π/4 of signal point arrangements “3”and “7” respectively become a center, the target phase convergent angleis equal to i·(4π/4)+3π/4.

Thus, digital signals of signal point arrangements “0” and “4” of phases0 and 4π/4 according to the BPSK modulation system at the transmissionside respectively converge into a position rotated by the above angle Θon reception-side I-Q phase plane. When Θ is equal to 3π/4 or 7π/4, thereceived-signal point according to the BPSK modulation system is broughtto either of positions of phases 3π/4 and 7π/4. Also in the case of BPSKmodulation, by detecting Θ and inversely rotating a phase by −Θ, a phasesame as that of the transmission side can be realized (absolute phasegeneration), the relation between a signal point arrangement and adigital signal can be made the same as that of the transmission side,and a received digital signal can be easily identified.

Moreover, as shown in FIG. 26, a frame-sync detecting/regeneratingcircuit 2 is configured by a BPSK demapper section 3, sync detectingcircuits 40 to 47, a frame-synchronizing circuit 5, an OR gate circuit53, and a frame-synchronizing-signal generator 6. As shown in FIG. 12, areceived-signal-phase-rotation-angle detecting circuit 8 is configuredby delay circuits 81 and 82, a 0°/180° phase rotating circuit 83,averaging circuits 84 and 85, and a received-phase judging circuit 86.

I and Q base-band signals I(8) and Q(8) output from the demodulatingcircuit 1 are input to the BPSK demapper section 3 of the frame-syncdetecting/regenerating circuit 2 in order to acquire, for example, aBPSK-modulated frame-synchronizing signal and a BPSK-demapped bit streamB0 is output. The BPSK demapper section 3 is configured by, for example,a ROM.

Then, a frame-synchronizing signal will be described. In case of thehierarchical transmission system, a frame-synchronizing signal istransmitted by being BPSK-modulated so that a necessary C/N isminimized. A frame-synchronizing signal configured by 20 bits has a bitstream of (S0S1 . . . S18S19)=(11101100110100101000) which aretransmitted in order starting with S0. Hereafter, a bit stream of aframe-synchronizing signal is also referred to as “SYNCPAT.” The bitstream is converted into a signal point arrangement “0” or “4” throughthe BPSK mapping shown in FIG. 13(3) at the transmission side and aconverted symbol stream is transmitted.

To acquire a frame-synchronizing signal of 20 bits to be BPSK-modulatedand transmitted, that is, 20 symbols, it is necessary to convertreceived symbols into bits through the BPSK demapping shown in FIG.27(1) inversely to the mapping to be converted at the transmission side.Therefore, as shown in FIG. 27(1), (0) is judged when a demodulatedsignal is received in a hatched area on reception-side I-Q phase planeand (1) is judged when the signal is received in a not-hatched area.That is, in FIG. 27(1), an output is classified into (0) or (1)depending on a judgement area in which the output is received out of twojudgement areas divided by a BPSK judgement border line shown by a boldline in FIG. 27(1) and thereby, it is assumed that BPSK demapping isperformed.

I and Q base-band signals I(8) and Q(8) are input to the BPSK demappersection 3 for performing BPSK demapping and the bit stream B0BPSK-demapped in the BPSK demapper section 3 is output. In thisspecification, a demapper denotes a circuit for performing demapping.The bit stream B0 is input to the sync detecting circuit 40 in which abit stream of a frame-synchronizing signal is acquired from the bitstream B0.

Then, the sync detecting circuit 40 is described by referring to FIG.28. The sync detecting circuit 40 has 20 D-flip-flops (hereafterreferred to as D-F/Fs) D19 to D0 connected in series and a 20-stageshift register is constituted by these D-F/Fs D19 to D0. The bit streamB0 is input to the D-F/F D19 and successively shifted up to the D-F/FD0. At the same time, predetermined logical inversion is applied topredetermined bits of outputs of the D-F/Fs D19 to D0 and then, theoutputs are input to an AND gate 51. When output states (D0D1 . . .D18D19) of the D-F/Fs D19 to D0 become (11101100110100101000), an outputSYNA0 of the AND gate 51 becomes a high potential. That is, when SYNCPATis acquired, the SYNA0 becomes a high potential.

The output SYNA0 of the sync detecting circuit 40 is input to aframe-synchronizing circuit 5 through an OR gate circuit 53. In theframe-synchronizing circuit 5, when it is confirmed that an output SYNAof the OR gate circuit 53 repeatedly becomes a high potential everycertain frame cycle, it is discriminated that a frame sync isestablished and a frame-synchronizing pulse is output every frame cycle.

In the case of a hierarchical transmission system to which a pluralityof modulation systems having necessary C/Ns different from each otherare time-multiplexed and repeatedly transmitted with frame, header datashowing their multiple configuration is multiplexed (TMCC pattern inFIG. 11(1)). The transmission-configuration identifying circuit 9extracts TMCC showing a multiple configuration from a bit stream after aBPSK demapper input from the frame-synchronizing circuit 5 after it isdiscriminated that frame sync is established in the frame-syncdetecting/regenerating circuit 2, decodes the TMCC, and outputs amodulation-system identifying signal DM showing to which modulationsystem the present I and Q base-band signals I and Q conform to theselector 16 and the like (refer to FIG. 11(2)).

Moreover, the received-signal-phase-rotation-angle detecting circuit 8detects a received-signal-phase rotation angle Θ in accordance with aregenerated frame-synchronizing signal output from theframe-synchronizing-signal generator 6 after it is discriminated thatframe sync is established in the frame-sync detecting/regeneratingcircuit 2 and outputs a three-bit received-signal-phase-rotation-anglesignal AR(3) to the remapper 7 and the selector 16 of the carrier-waveregenerating circuit 10.

After a modulation-system identifying signal DM is input from thetransmission-configuration identifying circuit 9 and areceived-signal-phase-rotation-angle signal AR(3) is input from thereceived-signal-phase-rotation-angle detecting circuit 8, the selector16 of the carrier-wave regenerating circuit 10 reads phase error dataΔφ(8) out of a phase error table corresponding to a modulation systemand a received-signal-phase rotation angle Θ and outputs the data Δφ(8)to the D/A converter 17. However, before outputting the data, theselector 16 reads phase error data Δφ(8) out of the phase error table 13for 8PSK.

Therefore, the demodulating circuit 1 always operates as an 8PSKdemodulating circuit before the transmission-configuration identifyingcircuit 9 identifies a multiple configuration and thereceived-signal-phase-rotation-angle detecting circuit 8 detects areceived-signal-phase rotation angle Θ. Thus, a phase of areceived-signal point rotates against the transmission side by Θ=m×π/4(m is one of integers 0 to 7) depending on phase states of the referencecarrier waves f_(c1) and f_(c2) regenerated by the carrier-waveregenerating circuit 10 of the demodulating circuit 1.

That is, as shown in FIG. 13(3), a demodulated frame-synchronizingsignal has the following eight phase states depending on a phase stateof the reference carrier wave f_(c1) or f_(c2): a case in which areceived-signal point of a symbol stream of a frame-synchronizing signalBPSK-mapped to signal point arrangement “0” for bit (0) or to signalpoint arrangement “4” for bit (1) at the transmission side appears onsignal point arrangement “0” or “4” similarly to the case of thetransmission side, a case in which the received-signal point appears onsignal point arrangement “1” or “5” phase-rotated by Θ=π/4, a case inwhich the received-signal point appears on signal point arrangement “2”or “6” phase-rotated by Θ=2π/4, a case in which the received-signalpoint appears on signal point arrangement “3” or “7” phase-rotated byΘ=3π/4, a case in which the received-signal point appears on signalpoint arrangement “4” or “0” phase-rotated by Θ=4π/4, a case in whichthe received-signal point appears on signal point arrangement “5” or “1”phase-rotated by Θ=5π/4, a case in which the received-signal pointappears on signal point arrangement “6” or “2” phase-rotated by Θ=6π/4,and a case in which the received-signal point appears on signal pointarrangement “7” or “3” phase-rotated by Θ=7π/4. Therefore, it must bepossible to acquire a frame-synchronizing signal demodulated in anyphase.

Therefore, as shown in FIG. 29, the BPSK demapper section 3 isconfigured by BPSK demappers 30 to 37 corresponding to phase rotationsof Θ=0 (m=0), Θ=π/4 (m=1), Θ=2π/4 (m=2), . . . , Θ=6π/4 (m=6), andΘ=7π/4 (m=7).

FIG. 27(2) shows BPSK demapping for a case in which a phase of a symbolstream of a demodulated frame-synchronizing signal rotates by Θ=π/4, andbit (0) appears on signal point arrangement “1” and bit (1) appears onsignal point arrangement “5.” A BPSK judgement border line shown by abold line in FIG. 27(2) rotates by π/4 counterclockwise from the BPSKjudgement border line shown by a bold line for BPSK demapping in FIG.27(1) in the case of reception at the same phase as the transmissionside. By using a BPSK demapper (refer to symbol 31 in FIG. 29) forperforming the BPSK demapping shown in FIG. 27(2), it is possible tostably acquire a frame-synchronizing signal phase-rotated by Θ=π/4. Abit stream BPSK-demapped by the BPSK demapper 31 serves as an output B1of the BPSK demapper section 3 in FIG. 26.

Similarly, BPSK demappers 32 to 37 perform BPSK demapping at BPSKjudgement border lines rotated by 2π/4, 3π/4, . . . , and 7π/4counterclockwise from the BPSK judgement border line shown by a boldline for the BPSK demapping in FIG. 27(1) to stably acquireframe-synchronizing signals phase-rotated by Θ=2π/4, 3π/4, . . . , and7π/4. Bit streams BPSK-demapped by the BPSK demappers 32 to 37 serve asoutputs B2 to B7 of the BPSK demapper section 3 in FIG. 26. The BPSKdemapper 30 performs BPSK demapping at the BPSK judgement border lineshown by a bold line for the BPSK demapping in FIG. 27(1) to stablyacquire a frame-synchronizing signal of Θ=0. A bit stream BPSK-demappedby the BPSK demapper 30 serves as an output B0 of the BPSK demappersection 3 in FIG. 26.

Configurations of sync detecting circuits 41 to 47 are the same as theconfiguration of the sync detecting circuit 40. By using these syncdetecting circuits 40 to 47, a frame-synchronizing signal is acquired byone of the sync detecting circuits 40 to 47 independently of phaserotation of a base-band signal according to a phase state of thereference carrier wave f_(c1) or f_(c2) regenerated by the carrier-waveregenerating circuit 10 of the demodulating circuit 1 and ahigh-potential SYNAn (n is one of integers 0 to 7) is transmitted fromthe sync detecting circuit acquiring the frame-synchronizing signal.

The SYNAn output from one of the sync detecting circuits 40 to 47 isinput to the OR gate circuit 53 and a logical sum SYNA of the SYNAn isoutput from the OR gate circuit 53. The frame-synchronizing circuit 5judges that frame sync is established when it is confirmed that a highpotential of SYNA is alternately repeatedly input every certain frameinterval and outputs a frame-synchronizing pulse FSYNC every framecycle. The frame-synchronizing-signal generator 6 generates a bit streamsame as a pattern SYNCPAT of a frame-synchronizing signal acquired bythe BPSK demapper 3, sync detecting circuits 40 to 47, andframe-synchronizing circuit 5 (the bit stream is referred to as aregenerated frame-synchronizing signal) in accordance with theframe-synchronizing pulse FSYNC output by the frame-synchronizingcircuit 5.

The process is described above in which a frame-synchronizing signal isacquired from I and Q symbol-stream data I(8) and Q(8) output from thedemodulating circuit 1 by the frame-sync detecting/regenerating circuit2 shown in FIG. 26 and a regenerated frame-synchronizing signal isoutput from the frame-synchronizing-signal generator 6 after a certaintime elapses.

Then, the transmission-configuration identifying operation by thetransmission-configuration identifying circuit 9 is described below. Thetransmission-configuration identifying circuit 9 inputs bit streams B0to B7 output by the BPSK demapper 3 of the frame-syncdetecting/regenerating circuit 2, SYNA0 to SYNA7 output by syncdetecting circuits 40 to 47, and a frame-synchronizing pulse FSYNCoutput by the frame-synchronizing circuit 5. Moreover, when the circuit9 inputs the frame-synchronizing pulse FSYNC, it captures a bit streamBn of a system repeatedly becoming a high potential in SYNA0 to SYNA7,extracts and decodes the TMCC pattern in FIG. 11(1) by using apredetermined timing signal generated in accordance with theframe-synchronizing pulse FSYNC, and outputs a modulation-systemidentifying signal DM showing on which modulation system the present Iand Q base-band signals I and Q depend (refer to FIG. 11(2)).

Then, absolute phase generation is described below which is realized byobtaining the present received-signal-phase rotation angle from a signalpoint arrangement of an acquired frame-synchronizing signal andinversely rotating the phase of demodulated I and Q base-band signalsI(8) and Q(8) in accordance with the obtained received-signal-phaserotation angle.

Each symbol of a symbol stream of a frame-synchronizing signal which isBPSK-mapped at the transmission side, transmitted, and demodulated to Iand Q base-band signals I(8) and Q(8) by the demodulating circuit 1 isdemapped to bit (0) or (1) by the BPSK demapper section 3 and thedifference between phases of a symbol demapped to bit (0) and a symboldemapped to bit (1) is equal to 180°.

Therefore, by rotating the phase of the symbol demapped to bit (1) atthe frame-synchronizing-signal portion of a received symbol stream by180°, symbol streams which are all demapped to bit (0) are obtained.

Moreover, by obtaining the average value of a plurality of symbols ofthe symbol streams which are all demapped to bit (0), areceived-signal-point arrangement for bit (0) of BPSK is obtained.Therefore, by obtaining the phase difference between the obtainedreceived-signal point for bit (0) of BPSK and the signal pointarrangement “0” mapped to bit (0) at the transmission side, assuming thephase difference as a received-signal-phase rotation angle Θ, andapplying phase rotation of η=−Θ to the whole demodulated I and Qbase-band signals, it is possible to generate absolute phases of I and Qbase-band signals I(8) and Q(8).

As described above, by receiving a frame-synchronizing pulse output fromthe frame-synchronizing circuit 5, the frame-synchronizing-signalgenerator 6 generates a bit stream same as the pattern SYNCPAT of anacquired frame-synchronizing signal and supplies the bit stream to the0°/180° phase-rotating circuit 83 of thereceived-signal-phase-rotation-angle detecting circuit 8 as aregenerated frame-synchronizing signal. The 0°/180° phase-rotatingcircuit 83 rotates the phase of I and Q base-band signals by 180° forbit (1) of a bit stream of a supplied regenerated frame-synchronizingsignal but the circuit 83 does not rotate the phase of I and Q base-bandsignals for bit (0) of the bit stream in accordance with a bit (0) or(1) of a bit stream of a supplied regenerated frame-synchronizingsignal.

The timing of a bit stream of a regenerated frame-synchronizing signaltransmitted from the frame-synchronizing-signal generator 6 is made tocoincide with the timing of a symbol stream of a frame-synchronizingsignal in I and Q symbol streams by the delay circuits 81 and 82 at theinput side of the 0°/180° phase-rotating circuit 83. The delay circuits81 and 82 respectively open their output gate only while aframe-synchronizing-signal-interval signal is output from theframe-synchronizing-signal generator 6. Therefore, I and Q symbolstreams DI(8) and DQ(8) of a frame-synchronizing-signal portion areoutput from the delay circuits 81 and 82. In case of the I and Q symbolstreams DI(8) and DQ(8), a symbol portion corresponding to bit (1) of abit stream of a regenerated frame-synchronizing signal is phase-rotatedby 180° by the 0°/180° phase-rotating circuit 83 but a symbol portioncorresponding to bit (0) is transmitted to the averaging circuits 84 and85 as symbol streams VI(8) and VQ(8) without being phase-rotated.Because all of 20 bits of the symbol streams VI(8) and VQ(8)constituting a frame-synchronizing signal are equal to bit (0), thesymbol streams VI(8) and VQ(8) serve as symbol streams when receiving asignal BPSK-mapped at the transmission side.

FIG. 30(1) shows the signal point arrangement of I and Q symbol streamsI(8) and Q(8) of a frame-synchronizing signal when received at areceived-signal-phase rotation angle Θ=0 and FIG. 30(2) shows the signalpoint arrangement of I and Q symbol streams VI(8) and VQ(8) afterconverted by the 0°/180° phase-rotating circuit 83. I and Q symbolstreams VI(8) and VQ(8) are transmitted to the averaging circuits 84 and85 and their quantization bit lengths are respectively converted into 16to 18 bits and then, quantization bit lengths for four frames(for16×4=64 symbols) are averaged, and the averaged value is output asAVI(8) and AVQ(8) according to the original quantization bit length of 8bits. In this case, I and Q symbol streams VI(8) and VQ(8) are averagedin order to stably obtain a signal point arrangement even if a slightphase change or amplitude fluctuation occurs in a received base-bandsignal due to deterioration of a received C/N occurs.

A received-signal point [AVI(8), AVQ(8)] of a signal obtained byBPSK-mapping bit (0) by the averaging circuits 84 and 85 is obtained.Then, the received-signal point [AVI(8), AVQ(8)] is input to thereceived-phase judging circuit 86 comprising a ROM and areceived-signal-phase rotation angle Θ is obtained in accordance with areceived-signal-phase-rotation-angle judging table on the AVI-AVQ phaseplane shown in FIG. 31 and a phase-rotation-angle signal AR(3) of threebits (natural binary number) corresponding to the Θ is output. R=0-7 inFIG. 31 shows a decimal notation of the phase-rotation-angle signalAR(3). For example, a received-signal-phase rotation angle obtained byjudging a signal point of the point Z=[AVI(8), AVQ(8)] shown in FIG. 30in accordance with a received-signal-phase-rotation-angle judging tableis equal to Θ=0. Therefore, R becomes equal to 0 and (000) istransmitted as the received-signal-phase-rotation-angle signal AR(3).When the received-signal-phase rotation angle Θ is equal to π/4, R=1 isobtained and (001) is transmitted as thereceived-signal-phase-rotation-angle signal AR(3).

Because the remapper 7 comprising a ROM receives thereceived-signal-phase-rotation-angle signal AR(3) to rotate the phase ofI and Q base-band signals I(8) and Q(8) in accordance with thereceived-signal-phase-rotation-angle signal AR(3), an absolute phase isgenerated.

Functions of the remapper 7 are described below. The remapper 7constitutes a phase converting circuit for making the signal pointarrangement of received I and Q base-band signals I(8) and Q(8) same asthat of the transmission side. A received-signal-phase rotation angle Θis calculated by the received-signal-phase-rotation-angle detectingcircuit 8 and a received-signal-phase-rotation-angle signal AR(3)corresponding to the received-signal-phase rotation angle Θ is suppliedto the remapper 7. In this case, the decimal notation R of thereceived-signal-phase-rotation-angle signal AR(3) is one of integers 0to 7 and the relation with the received-signal-phase rotation angle Θ isdefined as shown by the following expression (1).

R=Θ/(π/4)  (1)

In the above expression, Θ is equal to m·(π/4) and m is one of integers0 to 7.

Absolute phase generation for I and Q base-band signals is realized byapplying inverse rotation, that is, phase rotation of −Θ to areceived-signal-phase rotation angle Θ. Therefore, the remapper 7phase-rotates input I and Q base-band signals I and Q by an angle η(=−Θ) in accordance with the following expressions (2) and (3) andoutputs absolute-phase-generated I and Q base-band signals I′(8) andQ′(8) (hereafter referred to as I′ and Q′ by omitting the number ofquantization bits).

I′=I cos(η)−Q sin(η)  (2)

Q′=I sin(η)−Q cos(η)  (3)

Moreover, it is permitted that a frame-synchronizing signal is acquiredby the frame-sync detecting/regenerating circuit 2 and aframe-synchronizing pulse is output and thereafter, thetransmission-configuration identifying circuit 9 previously identifies atransmission configuration and then thereceived-signal-phase-rotation-angle detecting circuit 8 detects areceived-signal-phase rotation angle or thereceived-signal-phase-rotation-angle detecting circuit 8 previouslydetects the received-signal-phase rotation angle and then thetransmission-configuration identifying circuit 9 identifies thetransmission configuration. Moreover, it is possible to simultaneouslyperform the detection of a received-signal-phase rotation angle by thereceived-signal-phase-rotation-angle detecting circuit 8 and theidentification of a transmission configuration by thetransmission-configuration identifying circuit 9.

In case of the above-described conventional receiver, however, it isnecessary to prepare such seven phase error tables as the phase errortable 13 for correcting the phase of the reference carrier waves f_(c1)and f_(c2) for demodulation according to the 8PSK modulation system,phase error tables 14-1 and 14-2 for correcting the phase of thereference carrier waves f_(c1) and f_(c2) for demodulation according tothe QPSK modulation system, and phase error tables 15-1 to 15-4 forcorrecting the phase of the reference carrier waves f_(c1) and f_(c2)for demodulation according to the BPSK modulation system. Therefore,there is a problem that a necessary memory capacity increases.

It is an object of the present invention to provide a receiver requiringonly a small circuit size.

DISCLOSURE OF THE INVENTION

A receiver of the present invention comprises demodulating means fordemodulating a signal to be PSK-modulated in which digital signalsmodulated by 2-phase, 4-phase, and 8-phase PSK modulation systems aretime-multiplexed by using a carrier wave regenerated by carrier-waveregenerating means and outputting I and Q symbol-stream data in symbols;received-signal-phase-rotation-angle detecting means for detecting aphase rotation angle Θ of I and Q symbol-stream data against thetransmission side for each symbol output from the demodulating means,inversely-phase-rotating means for rotating the phase of I and Qsymbol-stream data for each symbol output from the demodulating means by−Θ against the phase rotation angle Θ detected by thereceived-signal-phase-rotation-angle detecting means, generating theabsolute phase of the phase of the I and Q symbol-stream data, andoutputting the absolute phase; and modulation-system identifying meansfor identifying a modulation system currently demodulated by thedemodulating means; wherein the inversely-phase-rotating means rotatesthe phase of the I and Q symbol-stream data for each symbol output fromthe demodulating means by two types of phase rotation angles throughtime sharing and outputs the data and one of the two types is assumed tobe equal to the above angle −Θ and the carrier-wave regenerating meansis provided with a phase error table storing carrier-wave-phase-errordata for various I and Q symbol-stream data sets after absolute phasegeneration by the 2-phase PSK modulation system and phase-errordetecting means for detecting a phase error of a regenerated carrierwave by obtaining a shift angle Θ′ of a received-signal point shown byan I and Q symbol-stream-data set for each symbol after absolute phasegeneration viewed in the positive direction or negative direction ofI-axis included in the phase error table up to a target phase convergentangle according to a modulation system identified by themodulation-system identifying means and reading carrier-wave-phase-errordata corresponding to an I and Q symbol-stream data set whenphase-rotating the other one of the two types to be phase-rotated byinversely-phase-rotating means by −(Θ+Θ′) through time sharing out of aphase error table so as to correct a phase of a regenerated carrier wavein accordance with carrier-wave-phase-error data detected by thephase-error detecting means.

Inversely-phase-rotating means outputs I and Q symbol-stream dataabsolute-phase-generated by phase-rotating I and Q symbol-stream datafor each symbol output from demodulating means by −Θ and moreover,outputs I and Q symbol-stream data phase-rotated by −(Θ+Θ′) through timesharing when assuming a shift angle up to a target phase convergentpoint of a received-signal point shown by an absolute-phase-generated Iand Q symbol-stream data set viewed in the positive or negativedirection of I-axis included in a phase error table in accordance with amodulation system identified by modulation-system identifying means asΘ′. Phase-error detecting means reads phase error data out of a phaseerror table by using the I and Q symbol-stream data set. Because thephase error data is data corresponding to a modulation system of areceived signal currently demodulated by demodulating means, areceived-signal-phase rotation angle against the transmission side, anda received-signal point, carrier-wave regenerating means requires onlyone phase error table. Therefore, it is possible to decrease the numberof phase error tables to be provided for carrier-wave regenerating meansand greatly simplify a circuit configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of an essentialportion of a wave-to-be-PSK-modulated receiver of an embodiment of thepresent invention;

FIG. 2 is an illustration of a domain of a phase error table in FIG. 1;

FIG. 3 is an illustration showing the relation betweenreceived-signal-point phase angle and phase error data in the phaseerror table in FIG. 1;

FIG. 4 is an illustration showing operations of a phase-error detectingcircuit;

FIG. 5 is an illustration showing operations of the phase-errordetecting circuit;

FIG. 6 is an illustration showing operations of the phase-errordetecting circuit;

FIG. 7 is a block diagram showing a configuration of the phase-errordetecting circuit;

FIG. 8 is a time chart showing operations of the phase-error detectingcircuit;

FIGS. 9(1) and 9(2) are illustrations showing operations of thephase-error detecting circuit;

FIG. 10 is an illustration of a domain of the phase error table of amodification of the present invention;

FIGS. 11(1) and 11(2) are illustrations showing frame configurations ofa hierarchical transmission system;

FIG. 12 is a block diagram showing a configuration around a demodulatingcircuit of a wave-to-be-PSK-modulated receiver according to aconventional hierarchical transmission system;

FIGS. 13(1) to 13(3) are illustrations showing signal point arrangementsfor PSK mapping;

FIG. 14 is a block diagram of a carrier-wave regenerating circuit inFIG. 12 locally omitted;

FIG. 15 is an illustration showing how to measure a phase of areceived-signal, point;

FIG. 16 is an illustration showing how to measure areceived-signal-phase rotation angle;

FIG. 17 is an illustration of a phase error table for 8PSK;

FIG. 18 is an illustration of a phase error table for QPSK;

FIG. 19 is the illustration of the phase error table for QPSK;

FIGS. 20(1) and 20(2) are illustrations for explaining relations betweenphase angles and target phase convergent angles of received-signalpoints for QPSK;

FIG. 21 is an illustration of a phase error table for BPSK;

FIG. 22 is an illustration of the phase error table for BPSK;

FIG. 23 is an illustration of a phase error table for BPSK;

FIG. 24 is an illustration of the phase error table for BPSK;

FIGS. 25(1) to 25(4) are illustrations for explaining relations betweenphase angles and target phase convergent angles of received-signalpoints for BPSK;

FIG. 26 is a block diagram of a sync detecting/regenerating circuit inFIG. 12;

FIGS. 27(1) and 27(2) are illustrations for explaining BPSK demapping;

FIG. 28 is a circuit diagram showing a configuration of a sync detectingcircuit in FIG. 26;

FIG. 29 is a circuit diagram showing a configuration of BPSK demappersin FIG. 26;

FIGS. 30(1) and 30(2) are signal point arrangement diagrams of aframe-synchronizing signal before and after passing through the 0°/180°phase rotating circuit in FIG. 12; and

FIG. 31 is an illustration of a received-signal-phase-rotation-anglediscriminating table used by the received-phase judging circuit in FIG.12.

BEST MODE FOR CARRYING OUT THE INVENTION

Then, an embodiment of the present invention will be described below byreferring to FIG. 1.

FIG. 1 is a block diagram of an essential portion of a broadcastreceiver (wave-to-be-PSK-modulated receiver) of the present invention,in which a component same as that in FIG. 12 is provided with the samesymbol.

In FIG. 12, the carrier-wave regenerating circuit has seven phase errortables 13, 14-1 and 14-2, and 15-1 to 15-4 and reads phase error datacorresponding to a set of I and Q symbol-stream data I(8) and Q(8)output from the demodulating circuit. In FIG. 1, however, thecarrier-wave regenerating circuit has only the phase error table 15-1Aand reads phase error data corresponding to an I and Q symbol-streamdata set absolute-phase-generated by a remapper 7A.

The remapper 7A generates the absolute phase of I and Q symbol-streamdata I(8) and Q(8) for each symbol output from the demodulating circuit1A by phase-rotating the data by −Θ in accordance with areceived-signal-phase rotation angle Θ detected by thereceived-signal-phase-rotation-angle detecting circuit 8 through timesharing and outputs the data as I and Q symbol-stream data RI(8)=RI₀(8)and RQ(8)=RQ₀(8) or outputs the I and Q symbol-stream data I(8) and Q(8)as I and Q symbol-stream data RI(8)=RI₁(8) and RQ(8)=RQ₁(8) by assuminga shift angle up to a target phase convergent angle of a received-signalpoint shown by I and Q symbol-stream data for each symbol afterabsolute-phase-generated by the remapper 7A viewed in the positivedirection of I-axis for each modulation system in accordance with anoutput of a phase-error detecting circuit to be described later as Θ′and phase-rotating the data by −(Θ+Θ′).

As shown in FIG. 8, by assuming that the demodulating circuit 1A outputsa new I and Q symbol-stream data set {I_(t)(8), Q_(t)(8)} in symbolssynchronously with a symbol clock CLK_(SYB) whenever the CLK_(SYB) isactivated at a time t (t= . . . , k−1, k, k+1, . . . ), the remapper 7Acaptures {I_(t)(8), Q_(t)(8)} at the inactivation timing of theCLK_(SYB) to output an I and Q symbol-stream data set {RI_(0t)(8),RQ_(0t)(8)} phase-rotated by −Θ and captures {I_(t)(8), Q_(t)(8)} at theactivation timing of the CLK_(SYB) to output an I and Q symbol-streamdata set {RI_(1t)(8), RQ_(1t)(8)} phase-rotated by −(Θ+Θ′). The former Iand Q symbol-stream data RI_(0t)(8) and RQ_(0t)(8) are latched by latchcircuits 68 and 69 at the inactivation timing of the CLK_(SYB) andoutput as absolute-phase-generated I and Q symbol-stream dataRI(8)′=RI_(0t)(8) and RQ(8)′=QI_(0t)(8).

The phase error table 15-1A provided for a carrier-wave regeneratingcircuit 10A is obtained by forming relations between various data setsof I and Q symbol-stream data RI(8) and RQ(8) (a range of RI(8)≧0)absolute-phase-generated by the remapper 7A in accordance with the BPSKmodulation system and 8 quantization bits (also referred to as phaseerror data of two's complement system) Δφ(8) into a ROM table, which isformed by using a range in which I coordinate on I-Q phase plane of Iand Q symbol-stream data RI(8) and RQ(8) is equal to or more than 0(refer to FIG. 2), in other words, a range of 0 to 2π/4 and a range of6π/4 to 8π/4 counterclockwise when viewed from a phase angle φ of areceived-signal point as a domain (refer to a solid line in FIG. 3).

Symbol 70 denotes a phase-error detecting circuit which obtains a shiftangle Θ′ of I and Q symbol-stream data I(8) and Q(8) in symbols outputfrom the demodulating circuit 1A up to a target phase convergent angleof a received-signal point shown by I and Q symbol-stream data RI₀(8)and RQ₀(8) for each symbol absolute-phase-generated by the remapper 7Aon the basis of the positive direction of I-axis for each modulationsystem of a received signal currently demodulated by the demodulatingcircuit 1A in accordance with RI₀(8) and RQ₀(8), high-order-three-bitdata Δφ₀(3) of phase error data Δφ(8)=Δφ₀(8) corresponding to a data setof I and Q symbol-stream data RI₀(8) and RQ₀(8) read out of the phaseerror table 15-1A, and a modulation-system identifying signal DM inputfrom the transmission-configuration identifying circuit 9 while theremapper 7A outputs the absolute-phase-generated I and Q symbol-streamdata RI(8)=RI₀(8) and RQ(8)=RQ₀(8) at the first half of one cycle of asymbol clock CLK_(SYB). Moreover, the circuit 70 calculates (Θ+Θ′) tooutput it to the remapper 7A and makes the remapper 7A output I and Qsymbol-stream data RI₁(8) and RQ₁(8) obtained by inverselyphase-rotating input I and Q symbol-stream data I(8) and Q(8) by −(Θ+Θ′)in order to detect a phase error. Then, the circuit 70 reads phase errordata Δφ(8)=Aφ1(8) corresponding to RI₁(8) and RQ₁(8) out of the phaseerror table 15-1 to output the data to the D/A converter 17.

In the case of the I and Q symbol-stream data RI₀(8) and RQ₀(8)absolute-phase-generated by the remapper 7A, received-signal points8PSK-mapped to signal point arrangements “0” to “7” at the transmissionside are respectively kept in any one of areas KR₀ to KR₇ eight-dividedabout phases 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4, 6π/4, and 7π/4 on the I-Qphase plane in FIG. 4. If a received-signal point P_(k) (RI_(0k),RQ_(0k)) of a symbol at a time t=k is kept in KR_(i) (i=0-7)(phase angleφ), a target phase convergent angle of the received-signal point P_(k)according to the phase correcting operation for the reference carrierwaves f_(c1) and f_(c2) by the carrier-wave regenerating circuit 10A isequal to i·(π/4). A shift angle Θ′ in the positive direction of I-axisbecomes equal to i·(π/4). In this case, phase error dataΔφ(8)=Δφ_(1k)(8) when inputting I and Q symbol-stream data RI_(1k)(8)and RQ_(1k)(8) obtained by inversely phase-rotating I and Qsymbol-stream data I_(k)(8) and Q_(k)(8) by −(Θ+Θ′) to the phase errortable 15-1A is the same as the phase error data for RI_(0k)(8) andRQ_(0k)(8) when viewed through a graph obtained by moving a solid linegraph in FIG. 3 by Θ′ in the positive direction of φ-axis.

For example, when the received-signal point P_(k) is kept in an area KR₂and a shift angle Θ′ is measured in the positive direction of I-axis,phase error data Δφ(8) is obtained which corresponds to RI_(0k)(8) andRQ_(0k)(8) when moving the solid line graph in FIG. 3 by 2π/4 in thepositive direction of φ-axis and replacing it with a broken-line graph.The portion of φ=3π/8 to 5π/8 of the broken-line graph in FIG. 3 is thesame as that of φ=3π/8 to 5π/8 corresponding to the area KR₂ in FIG. 17.The same is applied to a case in which i is not equal to 2. Therefore,phase error data corresponding to absolute-phase-generated I and Qsymbol-stream data I_(0k)(8) and Q_(0k)(8) in the phase error table inFIG. 17 is obtained by Δφ_(1k)(8). Because the I and Q symbol-streamdata I_(0k)(⁸) and Q_(0k)(8) are absolute-phase-generated, a targetphase convergent angle of a received-signal point P_(k) becomes same asa signal point arrangement of the transmission side and thus, acarrier-wave phase error to the received-signal point P_(k) according tothe 8PSK modulation system is correctly obtained independently of areceived-signal-phase rotation angle Θ.

Differently from the above described, in the case of I and Qsymbol-stream data R_(I0)(8) and R_(Q0)(8) absolute-phase-generated bythe remapper 7A, received-signal points QPSK-mapped to signal pointarrangements “1,” “3,” “5,” and “7” at the transmission side arerespectively kept in any one of areas ER₀ to ER₃ four-divided aboutphases π/4, 3π/4, 5π/4 and 7π/4 on the I-Q phase plane in FIG. 20(1). Ifthe received-signal point P_(k) of a symbol at a certain time t=k iskept in an ER_(i) (i=0-3), a target phase convergent angle of thereceived-signal point P_(k) according to the phase correcting operationto the reference carrier waves f_(c1) and f_(c2) by the carrier-waveregenerating circuit 10A is equal to i·(2π/4)+π/4. A shift angle Θ′ inthe positive direction of I-axis becomes i·(2π/4)+π/4. In this case,phase error data Δφ(8)=Δφ_(1k)(8) when inputting I and Q symbol-streamdata RI_(1k)(8) and RQ_(1k)(8) obtained by inversely phase-rotating Iand Q symbol-stream data I_(k)(8) and Q_(k)(8) by −(Θ+Θ′) to the phaseerror table 15-1A is the same as phase error data for RI_(0k)(8) andRQ_(0k)(8) when viewed through a graph obtained by moving the solid linegraph in FIG. 3 in the positive direction of φ-axis by Θ.

For example, when the received-signal point P_(k) is kept in the areaERo and a shift angle Θ′ is measured in the positive direction ofI-axis, phase error data Δφ(8) is obtained which corresponds toRI_(0k)(8) and RQ_(0k)(8) when moving the solid table in FIG. 3 by π/4in the positive direction of φ-axis and replacing the table with thegraph in FIG. 5. The portion of φ=0-2π/4 of the graph in FIG. 5 is thesame as the portion of φ=0-2π/4 corresponding to the area ER₀ in FIG.18. The same is applied to a case in which i is not equal to 0.Therefore, phase error data corresponding to absolute-phase-generated Iand Q symbol-stream data I_(0k)(8) and Q_(0k)(8) in the phase errortable in FIG. 18 is obtained by Δφ_(1k)(8). Because the I and Qsymbol-stream data I_(0k)(8) and Q_(0k)(8) are absolute-phase-generated,a target phase convergent angle of the received-signal point P_(k)becomes the same as a transmission-side signal point arrangement and acarrier-wave phase error to the received-signal point P_(k) according tothe QPSK modulation system is correctly obtained independently of areceived-signal-phase rotation angle Θ.

Moreover, in the case of I and Q symbol-stream data RI₀(8) and RQ₀(8)absolute-phase-generated by the remapper 7A, received-signal pointsBPSK-mapped to signal point arrangements “0” and “4” at the transmissionside are respectively kept in either of areas GR₀ and GR₁ two-dividedabout phases 0 and 4π/4 on the I-Q phase plane in FIG. 25(1). If thereceived-signal point P_(k) of a symbol is kept in a GR_(i) (i=0, 1) ata certain time t=k, a target phase convergent angle of thereceived-signal point P_(k) according to the phase correcting operationto the reference carrier waves f_(c1) and f_(c2) by the carrier-waveregenerating circuit 10A is equal to i·(4π/4). A shift angle Θ′ in thepositive direction of I-axis becomes i·(4π/4) (however, when measuringthe shift angle Θ′ in the negative direction of I-axis, the Θ′ becomesi·(4π/4)−π). In this case, phase error data Δφ(8)=Δφ_(1k)(8) wheninputting I and Q symbol-stream data RI_(1k)(8) and RQ_(1k)(8) obtainedby inversely phase-rotating I and Q symbol-stream data I_(k)(8) andQ_(k)(8) by −(Θ+Θ′) to the phase error table 15-1A is the same as phaseerror data for RI_(0k)(8) and RQ_(0k)(8) when viewed through a graphobtained by moving the solid line graph in FIG. 3 in the positivedirection of φ-axis by Θ′.

For example, when the received-signal point P_(k) is kept in the areaGR_(I) and a shift angle Θ′ is measured in the positive direction ofI-axis, phase error data Δφ(8) is obtained which corresponds toRI_(0k)(8) and RQ_(0k)(8) when moving the solid line graph in FIG. 3 byπ in the positive direction of φ-axis and replacing the graph with thegraph in FIG. 6. The portion of φ=2π/4−6π/4 of the graph in FIG. 6 isthe same as the portion of φ=2π/4−6π/4 corresponding to the area GRo inFIG. 21. The same is applied to a case in which i is equal to 0.Therefore, phase error data corresponding to absolute-phase-generated Iand Q symbol-stream data I_(0k)(8) and Q_(0k)(8) in the phase errortable in FIG. 21 is obtained by Δφ_(1k)(8). Because the I and Qsymbol-stream data I_(0k)(8) and Q_(0k)(8) are absolute-phase-generated,a target phase convergent angle of the received-signal point P_(k)becomes the same as a transmission-side signal point arrangement and acarrier-wave phase error to the received-signal point P_(k) according tothe BPSK modulation system is correctly obtained independently of areceived-signal-phase rotation angle Θ.

FIG. 7 is a block diagram showing a specific configuration of thephase-error detecting circuit 70 and FIG. 8 is a time chart showingoperations of the phase-error detecting circuit 70. The configuration ofthe phase-error detecting circuit 70 is described below by referring toFIG. 8. An angle Θ′ takes any one of 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4,6π/4, and 7π/4 which are respectively shown by one of two-bitthree-digit values such as (000), (001), (010), (011), (100), (101),(110), and (111) in order.

To make the description understandable, I and Q symbol-stream dataI_(k)(8) and Q_(k)(8) for one symbol output from the demodulatingcircuit 1A at a time t=k is described below as an example. The I_(k)(8)and Q_(k)(8) are output as a data set of RI_(k)(8)=RI_(0k)(8) andRQ_(k)(8)=Q_(0k)(8) rotated by −Θ through time sharing during one cycleof CLK_(SYB) and absolute-phase-generated by the remapper 7A and a dataset of RI_(k)(8)=I_(1k)(8) and RQ_(k)(8)=Q_(1k)(8) rotated by −(Θ+Θ′)through time sharing during one cycle of CLK_(SYB) by the remapper 7A.The former is latched by the latch circuits 68 and 69 and output to therear stage.

Symbols 71 and 72 in the phase-error detecting circuit 70 latch the signbit data serving as the MSB of RI_(0k)(8) and RQ_(0k)(8) output from theremapper 7A whenever a predetermined timing signal T1 is input andoutput the data as Ri(1)=Ri_(0k)(1) and Rq(1)=Rq_(0k)(1). Symbol 73denotes a selector which selects and outputs (000) showing Θ′=0 whenRI_(0k)(8) is equal to or larger than 0 or selects and outputs (100)showing Θ′=4π/4 when RI_(0k)(8) is smaller than 0 depending on thepositive or negative of RI_(0k)(8) shown by Ri_(0k)(1) and thereby, whenthe portion of the BPSK modulation system in a received signal accordingto the hierarchical transmission system is demodulated, outputs a shiftangle Θ′=BR_(BPSK)(3) up to a target phase convergent angle of areceived-signal point P_(k) shown by RI_(0k)(1) and RQ_(0k)(1) viewed inthe positive direction of I-axis. The selector 73 selects (000) becauseP_(k) is kept in the area GR₀ in FIG. 25(1) and the target phaseconvergent angle is equal to 0 when RI_(0k)(8) is equal to or largerthan 0 and selects (100) because P_(k) is kept in the area GR₁ in FIG.25(1) and the target phase convergent angle is equal to 4π/4 whenRI_(0k)(8) is smaller than 0.

Symbol 74 denotes a selector which selects and outputs (001) showingΘ′=π/4, (011) showing Θ′=3π/4, (101) showing Θ′=5π/4, or (111) showingΘ′=7π/4 in accordance with a combination of positive and negative ofRI_(0k)(8) and RQ_(0k)(8) shown by Ri_(0k)(1) and Rq_(0k)(1) andthereby, outputs a shift angle Θ′=BR_(QPSK)(3) up to a target phaseconvergent angle of the received-signal point P_(k) shown by RI_(0k)(1)and RQ_(0k)(1) viewed in the positive direction of I-axis when theportion of QPSK modulation system in a received signal according to thehierarchical transmission system is demodulated.

Specifically, the selector 74 selects (001) because P_(k) is kept in thearea ER₀ in FIG. 20(1) and a target phase convergent angle is equal toπ/4 when RI_(0k)(8) is equal to or larger than 0 and RQ_(0k)(8) is equalto or larger than 0 and selects (011) because P_(k) is kept in the areaER₁ in FIG. 20(1) and a target phase convergent angle is equal to 3π/4when RI_(0k)(8) is smaller than 0 and RQ_(0k)(8) is equal to or largerthan 0. Moreover, the selector 74 selects (101) because P_(k) is kept inthe area ER₂ in FIG. 20(1) and a target phase convergent angle is equalto 5π/4 when RI_(0k)(8) is smaller than 0 and RQ_(0k)(8) is smaller than0 and selects (111) because P_(k) is kept in the area ER₃ in FIG. 20(1)and a target phase convergent angle is equal to 7π/4 when RI_(0k)(8) issmaller than 0 and RQ_(0k)(8) is equal to or larger than 0.

Symbol 75 denotes an inverting circuit which outputs−RI_(k)(8)=−RI_(0k)(8) and −RQ_(k)(8)=−RQ_(0k)(8) obtained by invertingonly positive and negative of RI_(k)(8)=RI_(0k)(8) andRQ_(k)(8)=RQ_(0k)(8) though their absolute values are equal to eachother. A phase angle of a received-signal point shown by −RI_(0k)(8) and−RQ_(0k)(8) is equal to a value obtained by adding π to a phase angle φof a received-signal point shown by original RI_(0k)(8) and RQ_(0k)(8).Symbol 76 denotes a selector which directly inputs RI_(k)(8)=RI_(0k)(8)and RQ_(k)(8)=RQ_(0k)(8) to the phase error table 15-1A when RI_(0k)(1)shows RI_(0k)(8)≧0 while CLK_(SYB) is inactivated and makes the phaseerror table 15-1A output phase error data Δφ_(k)(8)=Δφ_(0k)(8)corresponding to RI_(0k)(8) and RQ_(0k)(8) and reads the data. However,when RI_(0k)(1) shows RI_(0k)(8)<0, the selector 76 inputs −RI_(0k)(8)and −RQ_(0k)(8) to be kept in the graph of the phase error table 15-1Ato the table 15-1A and makes the table 15-1A output phase error dataΔφ_(k)(8)=Δφ_(0k)(8) corresponding to −RI_(0k)(8) and −RQ_(0k)(8) toread the data Δφ_(k)(8).

Moreover, the selector 76 directly inputs RI(8) and RQ(8) output fromthe remapper 7A to the phase error table 15-1A while CLK_(SYB) isactivated and makes the table 15-1A output phase error data Δφ(8)corresponding to the RI(8) and RQ(8) to read the data Δφ(8).

Symbol 77 denotes a latch circuit which judges whether the absolutevalue of a phase error is larger or smaller than (π/8)+s (π/4) (s is 0or 1) in accordance with phase error data Δφ_(k)(3)=Δφ_(0k)(3) servingas high-order three bits of phase error data Δφ_(k)(8)=Δφ_(0k)(8) outputfrom the phase error table 15-1A whenever a predetermined timing signalT2 is input (refer to FIG. 3). By combining the Δφ_(k)(3) with sign bitdata RI_(0k)(1) serving as the MSB of RI_(0k)(8) and performing a simpleoperation, it is known in which area among eight areas KR₀ to KR₇ inFIG. 4 a received-signal point P_(k) shown by RI_(0k)(8) and RQ_(0k)(8)is kept when the portion of the 8PSK modulation system in a receivedsignal according to the hierarchical transmission system is demodulatedand it is possible to output a shift angle Θ′=BR_(8PSK)(3) up to atarget phase convergent angle of the received-signal point P_(k) shownby the RI_(0k)(8) and RQ_(0k)(8) viewed in the positive direction ofI-axis.

Symbol 78 denotes a four-bit adder for adding 4-bit data (however, carryto fifth bit is not performed) in which Ri(1)=Ri_(0k)(1) is input to themost significant bit of one input side and an output of a latch circuit74 is input to low-order three bits. Moreover, a selector 79 isconnected to the other input side of the adder 78 to output (0101) whenRI_(0k)(1) shows RI_(0k)(8)≧0 and outputs (1101) correspondingly to thefact that π is added to a phase angle φ of a received-signal point shownby RI_(0k)(8) and RQ_(0k)(8) when code inversion is performed by theinverting circuit 75 when the RI_(0k)(1) shows RI_(0k)(8)<0. Then, theadder 78 performs four-bit addition of two inputs. When the portion ofthe 8PSK modulation system in the added value whose high-order threebits serve as a received signal in accordance with a hierarchicaltransmission system is demodulated, the demodulated portion shows ashift angle Θ′ up to a target phase convergent angle of areceived-signal point P_(k) shown by RI_(0k)(1) and RQ_(0k)(1) viewed inthe positive direction of I-axis. Therefore, the adder 78 outputs theshift angle Θ′ as BR_(8PSK)(3).

Symbol 80 denotes a selector which outputs an input supplied from theselector 73 as BR(3) showing a shift angle Θ′ while the demodulatingcircuit 1A demodulates the BPSK-modulated portion, outputs an inputsupplied from the selector 74 as the BR(3) showing the shift angle Θ′while the demodulating circuit 1A demodulates the QPSK-modulatedportion, and outputs an input supplied from the selector 78 as the BR(3)showing the shift angle Θ′ while the demodulating circuit 1A demodulatesthe QPSK-modulated portion in accordance with a modulation-systemidentifying signal DM input from the transmission-configurationidentifying circuit 9. The BR(3) shows a shift angle Θ′ up to a targetphase convergent angle according to a modulation system currentlydemodulated by the demodulating circuit 1A of a received-signal pointP_(k) shown by the set data of absolute-phase-generated I and Qsymbol-stream data RI_(0k)(8) and RQ_(0k)(8) viewed in the positivedirection of I-axis while CLK_(SYB) is inactivated and in the periodafter the timing signal T2. Symbol 81 denotes a three-bit adder(however, carry to fourth bit is not performed) which adds areceived-signal-phase-rotation-angle detecting signal AR(3) output bythe received-signal-phase-rotation-angle detecting circuit 8 to anoutput of the selector 80.

Symbol 82 denotes a latch circuit which latches an output of the adder81 in accordance with a timing signal T3 input while CLK_(SYB) isinactivated and in the period after the timing signal T2 and outputsCR(3) showing (Θ+Θ′) to the remapper 7A. When the CLK_(SYB) isactivated, the remapper 7A outputs RI_(1k)(8) and RQ_(1k)(8) whosephases are rotated by −(Θ+Θ′) against I_(k)(8) and Q_(k)(8). TheRI_(1k)(8) and RQ_(1k)(8) are input to the phase error table 15-1Athrough the selector 76 and corresponding phase error dataΔφ_(k)(8)=Δφ_(1k)(8) is read. The Δφ_(1k)(8) is latched by a latchcircuit 83 in accordance with a timing signal T4 and output to the D/Aconverter 17 as Δφ(8)′=Δφ_(1k)(8)′. Other components are completely thesame as those in FIG. 12.

Then, operations of the above-described embodiment are briefly describedbelow.

(1) Start of Reception

At start of reception, the received-signal-phase-rotation-angledetecting circuit 8 outputs AR(3)=(000) corresponding to areceived-signal-phase rotation angle Θ=0 as an initial value before afirst received-signal-phase rotation angle can be detected and thetransmission-configuration identifying circuit 9 outputs amodulation-system identifying signal DM corresponding to 8PSK modulationas an initial value before a first modulation system can be identified.

The remapper 7A outputs RI_(0t)(8)(=I_(t)(8)) and RQ_(0t)(8)(=Q_(t)(8))phase-rotated by −Θ at the first half of one cycle of a symbol clockCLK_(SYB) against I_(t)(8) and Q_(t)(8) in symbols output at a time t(t= . . . , k−1, k, k+1, . . . ) from the demodulating circuit 1A andthe RI_(0t)(8) and RQ_(0t)(8) are latched by the latch circuits 68 and69 and output to the rear stage. Before the phase-error detectingcircuit 70 detects a received-signal-phase rotation angle by thereceived-signal-phase-rotation-angle detecting circuit 8 and identifiesa modulation system by the transmission-configuration identifyingcircuit 9, the selector 80 selects an output BP_(8PSK)(3) of the adder78 and outputs it as BR(3). Because AR(3) is (000), CR(3)=BP_(8PSK)(3)is input to the remapper 7A.

The BP_(8PSK)(3) shows a shift angle Θ′ up to a target phase convergentangle of a received-signal point P_(0t) shown by RI_(0t)(1) andRQ_(0t)(1) viewed in the positive direction of I-axis when regardingthat every received signal follows the 8PSK modulation system (refer toFIG. 9(1)). Therefore, a received-signal point P_(1t) according toRI_(1t)(1) and RQ_(1t)(1) phase-rotated by the remapper 7A by −(Θ+Θ′)shown by CR(3) is kept in a range of π/4 about a phase 0 on I-Q phaseplane as shown in FIG. 9(2). Moreover, because the difference betweenthe phase angle φ_(0t) and a target phase convergent angle of thereceived-signal point P_(0t) is equal to the phase angle φ_(1t) of thereceived-signal point P_(1t), the phase-error detecting circuit 70 isable to output correct phase error data Δφ_(t)(8)′=Δφ_(1t)(8) to the D/Aconverter 17 when regarding that the data follows the 8PSK modulationsystem by reading phase error data Δφ_(1t)(8) corresponding toRI_(1t)(1) and RQ_(1t)(1) out of the phase error table 15-1A andlatching the data Δφ_(1t)(8).

The data Δφ_(1t)(8) is converted into a phase error voltage by the D/Aconverter 17 and then, low-frequency components are extracted from thevoltage by the LPF 18, and the voltage is applied to the VCO 11 as acontrol voltage. When the phase error data Δφ_(1t)(8) is equal to 0,outputs of the LPF 18 are not changed or phases of the reference carrierwaves f_(c1) and f_(c2) are not changed. However, when phase error dataΔφ(8) is positive, outputs of the LPF 18 are strengthened and the phaseof the reference carrier waves f_(c1) and f_(c2) is delayed. However,when the phase error data Δφ(8) is negative, outputs of the LPF 18 areweakened and the phase of the reference carrier waves f_(c1) and f_(c2)is advanced. Thereby, the phase of the reference carrier waves f_(c1)and f_(c2) converges so as to keep a certain relation with a phase ofreceived carrier wave. As a result, the demodulating circuit 1A outputsI_(t)(8) and Q_(t)(8) obtained by converging digital signals of signalpoint arrangements “0” to “7” of phases 0, π/4, 2π/4, 3π/4, 4π/4, 5π/4,6π/4, and 7π/4 at the transmission side on a position rotated by Θ=m×π/4(m is any one of integers 0 to 7) on the reception-side I-Q phase plane.

The frame-sync detecting/regenerating circuit 5 acquires aframe-synchronizing signal in accordance with I_(t)(8) and Q_(t)(8) andoutputs a frame-synchronizing pulse, regenerated frame-synchronizingsignal, and frame-synchronizing-signal-interval signal. Thereceived-signal-phase-rotation-angle detecting circuit 8 detects areceived-signal-phase rotation angle Θ (this is shown as Θ_(w) in orderto distinguish Θ from initial value=0) viewed through I_(t)(8) andQ_(t)(8) against the transmission side by using I_(t)(8) and Q_(t)(8), aregenerated frame-synchronizing signal, and aframe-synchronizing-signal-interval signal and outputs AR(3) showing theΘ_(w) to the remapper 7A and phase-error detecting circuit 70. Whenreceiving a frame-synchronizing pulse FSYNC, thetransmission-configuration identifying circuit 9 captures a bit streamBn of a system repeatedly becoming a high potential among SYNA0 toSYNA7, extracts the TMCC pattern in FIG. 11(1) by using a predeterminedtiming signal generated from a frame-synchronizing pulse FSYNC anddecodes the pattern, and outputs a modulation-system identifying signalDM showing which modulation system the present I_(t)(8) and Q_(t)(8)depend on (refer to FIG. 11(2)).

In this case, when assuming that the received-signal-phase rotationangle Θ_(w) is previously detected, the remapper 7A outputsabsolute-phase-generated I_(0t)(8) and Q_(0t)(8) obtained by inverselyphase-rotating I_(t)(8) and Q_(t)(8) by −Θ_(w). Because CR(3) output bythe phase-error detecting circuit 70 is equal to (Θ_(w)+Θ′), areceived-signal point P_(1t) according to RI_(1t)(1) and RQ_(1t)(1)shown by CR(3) phase-rotated by −(Θ_(w)+Θ′) by the remapper 7A is keptin a range of π/4 about a phase 0 on I-Q phase plane as shown in FIG.9(2) even if Θ changes from an initial value 0 to Θ_(w). Moreover,because the difference between phase angle φ_(0t) and target phaseconvergent angle of received-signal point P_(0t) is equal to the phaseangle φ_(1t) of the received-signal point P_(1t), the phase-errordetecting circuit 70 is able to output the correct phase error dataΔφ_(t)(8)′=Δφ_(1t)(8) to the D/A converter 17 when regarding that thedata follows the 8PSK modulation system by receiving phase error dataΔφ_(1t)(8) corresponding to RI_(1t)(1) and RQ_(1t)(1) from the phaseerror table 15-1A and latching the data Δφ_(1t)(8).

(2) Normal Receiving Operation

Hereafter, the normal receiving operation is described by assuming that,for example, Θ_(w) is equal to 3π/4 (AR(3)=(011)).

(i) 8PSK-modulation-system Portion (Refer to FIG. 9.)

When the transmission-configuration identifying circuit 9 identifies amultiple configuration and outputs a modulation-system identifyingsignal DM showing in which modulation-system portion the present I and Qsymbol streams I_(t)(8) and Q_(t)(8) output from the demodulatingcircuit 1A are included after operations of thereceived-signal-phase-rotation-angle detecting circuit 8, the selector80 of the phase-error detecting circuit 70 selects and outputs an outputof the adder 78 when the DM shows 8PSK. A received-signal point of adigital signal (abc) 8PSK-mapped to a transmission-side signal pointarrangement “3” is kept in a range of π/4 about a phase 6π/4 of a signalpoint arrangement “6” when viewed through, for example, Θ_(w)=3π/4 andI_(t)(8) and Q_(t)(8) serving as outputs of the demodulating circuit 1A.However, a received-signal point P_(0t) according to outputs I_(0t)(8)and Q_(0t)(8) of the remapper 7A is kept in a range of π/4 about thephase 3π/4 of the signal point arrangement “3” due to absolute phasegeneration similarly to the case of the transmission side.

In this case, because BR(3)=BP_(8PSK)(3) is set to (011) showing Θ′=3π/4and (Θ_(w)+Θ′)=6π/4, a received-signal point P_(1t) according toI_(1t)(8) and Q_(1t)(8) is kept in a range of π/4 about a phase 0.Because the difference between the phase angle φ_(0t) and a target phaseconvergent angle of the received-signal point P_(0t) is equal to thephase angle φ_(1t) of the received-signal point P_(1t), the phase-errordetecting circuit 70 is able to output phase error data for convergingreceived-signal points viewed through RI_(0t)(8) and RQ_(0t)(8) into aphase 3π/4 to a D/A converter 18 by reading phase error data Δφ_(1t)(8)corresponding to RI_(1t)(8) and RQI_(t)(8) out of the phase error table15-1A and latching the data Δφ_(1t)(8). Also for digital signals (abc)8PSK-mapped to other signal point arrangements “0,” “1,” “2,” “4,” “5,”“6,” and “7” at the transmission side, the circuit 70 is able to outputphase error data for converging received-signal points viewed throughoutputs RI_(0t)(8) and RQ_(0t)(8) of the remapper 7A into phases 0, π/4,2π/4, 4π/4, 5π/4, 6π/4, and 7π/4 to the D/A converter 18 in thecompletely same manner as the above described.

(ii) QPSK-modulation-system Portion

The selector 80 of the phase-error detecting circuit 70 selects andoutputs an output of the selector 74 when DM shows QPSK. For example, areceived-signal point of a digital signal (de) QPSK-mapped to atransmission-side signal point arrangement “7” is kept in a range of2π/4 about a phase 2π/4 of a signal point arrangement “2” when viewedthrough I_(t)(8) and Q_(t)(8) which are outputs of the demodulatingcircuit 1A. However, a received-signal point P_(0t) according to outputsI_(0t)(8) and Q_(0t)(8) of the remapper 7A is kept in a range of 2π/4about a phase 7π/4 of the signal point arrangement “7” due to absolutephase generation similarly to the case of the transmission side.

In this case, because BR(3)=BR_(QPSK)(3) becomes (111) showing Θ′=7π/4and (Θ_(w)+Θ′) is equal to 2π/4, a received-signal point P_(1t)according to I_(1t)(8) and Q_(1t)(8) is kept in a range of 2π/4 about aphase 0. Because the difference between the phase angle φ_(0t) and atarget phase convergent angle of a received-signal point P_(0t) is equalto the phase angle φ_(1t) of the received-signal point P_(1t), thephase-error detecting circuit 70 is able to output phase error data forconverging a received-signal point viewed through RI_(0t)(8) andRQ_(0t)(8) into a phase 7π/4 to the D/A converter 18 by reading phaseerror data Δφ_(1t)(8) corresponding to RI_(t)(8) and RQ_(1t)(8) out ofthe phase error table 15-1A and latching the data Δφ_(1t)(8). Also fordigital signals (de) QPSK-mapped to other signal point arrangements “1,”“3,” and “5” at the transmission side, the circuit 70 is able to outputphase error data for converging received-signal points viewed throughoutputs RI_(0t)(8) and RQ_(0t)(8) of the remapper 7A into phases π/4,3π/4, and 5π/4 to the D/A converter 18 in the completely same manner asthe above.

(iii) BPSK-modulation-system Portion

The selector 80 of the phase-error detecting circuit 70 selects andoutputs an output of the selector 74 when DM shows QPSK. For example, areceived-signal point of a digital signal (f) BPSK-mapped to atransmission-side signal point arrangement “1” is kept in a range of4π/4 about a phase 7π/4 of a signal point arrangement “7” when viewedthrough I_(t)(8) and Q_(t)(8) which are outputs of the demodulatingcircuit 1A. However, a received-signal point Pot according to outputsI_(0t)(8) and Q_(0t)(8) of the remapper 7A is kept in a range of 4π/4about a phase 7π/4 of the signal point arrangement “1” due to absolutephase generation similarly to the case of the transmission side.

In this case, because BR(3)=BR_(BPSK)(3) becomes (100) showing Θ′=4π/4and (Θ_(w)+Θ′) is equal to 7π/4, a received-signal point P_(1t)according to I_(1t)(8) and Q_(1t)(8) is kept in a range of 4π/4 about aphase 4π/4. Because the difference between a phase angle φ_(0t) and atarget phase convergent angle of a received-signal point P_(0t) is equalto the phase angle φ_(1t) of the received-signal point P_(1t), thephase-error detecting circuit 70 is able to output phase error data forconverging a received-signal point viewed through RI_(0t)(8) andRQ_(0t)(8) into a phase 4π/4 to the D/A converter 18 by reading phaseerror data Δφ_(1t)(8) corresponding to RI_(t)(8) and RQ_(1t)(8) out ofthe phase error table 15-1A and latching the data Δφ_(1t)(8). Also for adigital signal BPSK-mapped to a signal point arrangement “0” at thetransmission side, the circuit 70 is able to output phase error data forconverging received-signal points viewed through outputs RI_(0t)(8) andRQ_(0t)(8) of the remapper 7A into a phase 0 to the D/A converter 18 inthe completely same manner as the above.

The received-signal-phase-rotation-angle detecting circuit 8 repeatedlydetects a received-signal-phase rotation angle. Also when Θ_(w) has avalue other than 3π/4, the phase-error detecting circuit 70 completelysimilarly operates. Therefore, the circuit 70 is able to output phaseerror data for converging a received-signal point viewed from the outputside of the remapper 1A into a phase same as that of the transmissionside to the D/A converter 18 independently of a modulation system or avalue Θ_(w) of an original digital signal.

According to this embodiment, the remapper 7A outputs I and Qsymbol-stream data lot and Q_(0t) absolute-phase-generated by inverselyphase-rotating I and Q symbol-stream data I_(t) and Q_(t) for eachsymbol output from the demodulating circuit 1A by −Θ and moreover,outputs I and Q symbol-stream data I_(1t) and Q_(1t) inverselyphase-rotated by −(Θ+Θ′) by assuming a shift angle up to a target phaseconvergent angle of a received-signal point shown by anabsolute-phase-generated I and Q symbol-stream data set viewed in thepositive direction or negative direction of I-axis included in a phaseerror table for each modulation system through time sharing as Θ′. Byusing the set of the I and Q symbol-stream data I_(1t) and Q_(1t), thephase-error detecting circuit 70 reads phase error data Δφ_(1t)(8) outof the phase error table 15-1A. The phase error data Δφ_(1t)(8) servesas data corresponding to a modulation system of a received signalcurrently demodulated by the demodulating circuit 1A, areceived-signal-phase rotation angle Θ against the transmission sideviewed from an output point of the demodulating circuit 1A, and a phaseangle φ of a received-signal point. Therefore, it is enough to provideonly one phase error table for the carrier-wave regenerating circuit 10Aand thus, it is possible to decrease the number of phase error tables tobe provided for the carrier-wave regenerating circuit 10A and greatlysimplify a circuit configuration.

In the case of the above embodiment, a table using an area of I≧0 of I-Qphase plane as a domain is provided for the phase error table 15-1A.However, it is also permitted to provide a table using an area of I≦0 asa domain for the phase error table 15-1A (refer to FIG. 10). In thiscase, BR(3) output by the selector 80 of the phase-error detectingcircuit 70 is set so as to show a shift angle Θ′ up to a target phaseconvergent angle of a received-signal point shown by I and Qsymbol-stream data for each symbol after absolute-phase-generated by theremapper 7A viewed in the negative direction of I-axis according to amodulation system currently demodulated by a demodulating circuit.

Specifically, it is preferable to set the selector 73 in FIG. 7 so as tooutput (100) when an output Ri(1) of the latch circuit 71 shows anoutput RI(8)>0 of the remapper 7A and output (000) when the output Ri(1)shows RI(8)≦0; set the selector 74 so as to select and output (001) forRI(8)<0 and RQ(8)<0, (011) for RI(8)≧0 and RQ(8)<0, (101) for RI(8)≧0and RQ(8)≧0, (111) for RI(8)<0 and RQ(8)≧0 in accordance with thecombination of positive and negative of RI(8) and RQ(8) shown by theoutputs Ri(1) and Rq(1) of the latch circuits 71 and 72; and set theselector 76 so as to directly input the outputs RI(8) and RQ(8) of theremapper 7A to the phase error table 15-1A when Ri(1) shows RI(8)≦0 andinput −RI(8) and −RQ(8) serving as the outputs of the inverting circuit75 to the phase error table 15-1A when Ri(1) shows RI(8)≧0 whileCLK_(SYB) is inactivated. Moreover, while the CLK_(SYB) is activated, itis preferable to set the selector 76 so as to directly input RI(8) andRQ(8) output from the remapper 7A to the phase error table 15-1A.

Furthermore, it is permitted to provide a table using the whole area ofI-Q phase plane as a domain for the phase error table 15-1A. In thiscase, it is preferable to set the BR(3) output by the selector 80 of thephase-error detecting circuit 70 so as to show a shift angle Θ′ up to atarget phase convergent angle of a received-signal point shown by I andQ symbol-stream data for each symbol after absolute-phase-generated bythe remapper 7A viewed in either of the positive direction and negativedirection of I-axis according to a modulation system currentlydemodulated by a demodulating circuit. For example, to show a shiftangle Θ′ viewed in the positive direction of I-axis, it is preferable toomit the selector 73 in FIG. 7, input BR_(BPSK)(3)=(000) to the selector80; set the selector 74 so as to select and output (001) for RI(8)≧0 andRQ(8)≧0, (011) for RI(8)<0 and RQ(8)≧0, (101) for RI(8)<0 and RQ(8)<0,and (111) for RI(8)≧0 and RQ(8)<0 in accordance with the combination ofpositive and negative of RI(8) and RQ(8) shown by Ri(1) and Rq(1); omitthe inverting circuit 75 and selector 76 to directly input the outputsRI(8) and RQ(8) of the remapper 7A to the phase error table 15-1A; andomit the selector 79 to input a fixed value (0101) to the adder 78.

INDUSTRIAL APPLICABILITY

According to the present invention, it is enough to provide only onephase error table for carrier-wave regenerating means and thereby, it ispossible to decrease the number of phase error tables to be provided forthe carrier-wave regenerating means and greatly simplify a circuitconfiguration.

What is claimed is:
 1. A receiver comprising: demodulating means fordemodulating a signal to be PSK-modulated in which digital signalsmodulated by a plurality of PSK modulation systems having a differentnumber of phases are time-multiplexed by using carrier waves regeneratedby carrier-wave regenerating means and outputting symbol data;received-signal-phase-rotation-angle detecting means for detecting aphase rotation angle of each symbol data output from the demodulatingmeans against the transmission side; inversely-phase-rotating means forinversely rotating the phase of each symbol data output from thedemodulating means by a phase rotation angle detected by thereceived-signal-phase-rotation-angle detecting means and thereby,absolute-phase-generating the phase of each symbol data and outputtingthe phase; and modulation-system identifying means for identifying amodulation system currently demodulated by the demodulating means;characterized in that the inversely-phase-rotating means rotates thephase of each symbol data output from the demodulating means by twotypes of phase rotation angles through time sharing and outputs thephase rotation angles and one of the two types is equal to the inversephase rotation angle, the carrier-wave regenerating means is providedwith a phase error table storing carrier-wave phase error data forvarious symbol data after absolute-phase-generated according to the PSKmodulation system having the minimum number of phases and phase-errordetecting means for detecting a phase error of a regenerated carrierwave by obtaining a shift angle up to a target phase convergent angle ofa received-signal point shown by the absolute-phase-generated symboldata for each symbol viewed in the positive direction or negativedirection of I-axis included in a phase error table according to amodulation system identified by the modulation-system identifying meansand reading carrier-wave phase error data corresponding to symbol datainversely phase-rotated by an angle corresponding to the sum of theother phase rotation angle of the two types of phase rotation angles ofeach symbol data and a shift angle up to a target phase convergent angleagainst the transmission side phase-rotated by theinversely-phase-rotating means through the time sharing out of a phaseerror table, and a phase of a regenerated carrier wave is corrected inaccordance with the carrier-wave phase error data detected by thephase-error detecting means.
 2. A receiver comprising: demodulatingmeans for demodulating a signal to be PSK-modulated in which digitalsignals modulated in accordance with 2-phase, 4-phase, and 8-phase PSKmodulation systems are time-multiplexed by using carrier wavesregenerated by carrier-wave regenerating means and outputting I and Qsymbol-stream data for each symbol; received-signal-phase-rotation-angledetecting means for detecting a phase rotation angle Θ of I and Qsymbol-stream data for each symbol output from the demodulating meansagainst the transmission side; inversely-phase-rotating means forrotating a phase of I and Q symbol-stream data for each symbol outputfrom the demodulating means by −Θ against a phase rotation angle Θdetected by the received-signal-phase-rotation-angle detecting means,generating the absolute phase of the I and Q symbol-stream data, andoutputting the data; and modulation-system identifying means foridentifying a modulation system currently demodulated by thedemodulating means; characterized in that the inversely-phase-rotatingmeans rotates a phase of I and Q symbol-stream data for each symboloutput from the demodulating means by only two types of phase rotationangles through time sharing and outputs the phase of the I and Qsymbol-stream data, and one of the two types of the phase rotationangles is equal to the above −Θ, the carrier-wave regenerating means isprovided with a phase error table storing carrier-wave phase error datafor various I and Q symbol-stream data sets afterabsolute-phase-generated by the 2-phase PSK-modulation system andphase-error detecting means for detecting a phase error of a regeneratedcarrier wave by obtaining a shift angle Θ′ up to a target phaseconvergent angle of a received-signal point shown by anabsolute-phase-generated I and Q symbol-stream data set for each symbolviewed in the positive direction or negative direction of I-axisincluded in a phase error table according to a modulation systemidentified by the modulation-system identifying means and readingcarrier-wave phase error data corresponding to an I and Q symbol-streamdata set phase-rotated by −(Θ+Θ′) as the other one of the two typesphase-rotated by the inversely-phase-rotating means through the timesharing out of a phase error table, and a phase of a regenerated carrierwave is corrected in accordance with the carrier-wave phase error datadetected by the phase-error detecting means.